Implementation of Iir Digital Filters in Fpga
نویسندگان
چکیده
The problem of mapping data flow graphs (DFGs) of infinite impulse responce (IIR) filtering algorithms into application specific structure is considered. Methods of optimization of DFGs are considered for the purpose of finding IIR filter structures with the high throughput and hardware utilization. Optimization method is proposed which takes into account structural properties of FPGA, minimize its hardware volume, and provide designing pipelined structures with high clock frequency. This method was used by designing filter structures which form a library. This library contains a set of parametrized IIR filter structures and is intended to computer aided design of digital signal processing systems on the base of FPGAs. The filter structures are described by VHDL and have high throughput, hardware utilization and minimized sensitivity to truncation errors.
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